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CXL1510M
CCD Delay Line for Multi System For the availability of this product, please contact the sales office.
Description The CXL1510M is an IC developed for use in conjunction with Y/C signal processing ICs for multi systems. This CCD delay line provides the comb filter output for eliminating the chrominance signal cross talk and 1H delay output for luminance signals. Features * Single power supply (5V) * Built-in quadruple progression PLL circuit * Comb filter characteristics selectable * Delay time for 1H delay output selectable * Built-in peripheral circuits * Positive phase signal input, positive phase signal output Functions * Comb filter output * 1H delay output for luminance signal * Clock driver * Autobias circuit * Input clamp circuit (for luminance signals) * Center bias circuit (for chrominance signals) * Sample-and-hold circuit * Quadruple progression PLL circuit * Luminance signal delay time/comb filter characteristics selection circuit * Clock buffer output circuit Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD +6 V * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD 500 mW Recommended Operating Voltage (Ta = 25C) VDD 5V 5% Structure CMOS-CCD 24 pin SOP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94804-ST
CXL1510M
Recommended Clock Conditions (Ta = 25*C) * Input clock amplitude VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.) * Clock frequency fCLK 3.579545MHz * Input clock waveform sine wave Input Signal Amplitude Vsig 350mVp-p (Typ.), 575mVp-p (Max.)
Block Diagram and Pin Configuration (Top View)
PCOUT CONT1
C-OUT
AB-C
(NC)
(NC)
Vss
VCOIN
AB-P
(NC)
24
23
22
21
20
19
18
17
16
15
14
13
PLL fsc buffer Selector 1 Timing
D Output circuit (S/H) Autobias circuit (C) 1H/2H + D
Driver 1 Autobias circuit (Y)
Driver 2
Bias circuit
Bias circuit
Selector 2
Clamp circuit
1H
Output circuit (S/H)
1
2
3
4
5
6
7
8
9
10
11
12
CONT2
(NC)
VDD
C-IN1
(NC)
(NC)
Y-IN
Vss
Y-OUT
C-IN2
-2-
(NC)
CLK
Vss
fsc
CXL1510M
SOP 24pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS C-IN1 VDD C-IN2 (NC) CONT2 Y-IN (NC) Y-OUT (NC) (NC) CLK VSS VCOIN PCOUT (NC) (NC) (NC) AB-P fsc AB-C CONT1 C-OUT VSS I/O -- I -- I -- I I -- O -- -- I -- I O -- -- -- O O O I O -- Clock input GND VCO input Phase comparator output -- -- -- Autobias output (P) fsc buffer output Autobias output (C) Control 1 input Chrominance signal output GND GND Chrominance signal input 1 Power supply Chrominance signal input 2 -- Control 2 input Luminance signal input -- Luminance signal output -- -- Description
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CXL1510M
Description of Functions The CXL1510M enables the chrominance comb filter characteristics and luminance signal delay time to be selected using the control 1 and control 2 statuses. CONT1 CONT2 Mode (typical example) L L H H L H L H PAL/GBI PAL/M -- NTSC/M Chrominance comb filter characteristics 2H + 12 (1832bit) 2H (1820bit) -- 1H (910bit) Luminance signal delay time (number of CCD bits) 1H + 6 (914bit) 1H (908bit) -- 1H (908bit)
CONT1/CONT2 Input Level L/H L H Min. -- 2.0 Typ. 0 5.0 Max. 0.5 6.0 Unit V
* fsc Output Pin The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a 2.2k pull-down resistor when the fsc output is to be used.
fsc
fsc
VDD
2.2k
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CXL1510M
Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave) See Electrical Characteristics Measurement Circuit Item Symbol IDD1 Supply current IDD2 IDD3 -- Measurement condition 1 b b b SW condition 2 b b b 3 b b b 4 a a b 5 a b b 6 7 8 Min. Typ. Max. Unit Note
a ---- a ---- a ---- 35 50 mA 1
Chrominance Signal Characteristics (No signals input to Y-IN) Item Low frequency gain Symbol GLC1 GLC2 GLC3 FC1 Frequency response FC2 FC3 LIC1 Linearity LIC2 LIC3 Comb depth min. gain CCD1 CCD2 CCD3 SNC1 SN ratio SNC2 SNC3 CPC1 Coupling level Delay time CPC2 CPC3 DC (See Note 8) (See Note 7) 50% white video signal (See Note 5) (See Note 4) (See Note 3) (See Note 2) Measurement condition 1 a a a a a a a a a a a a a a a b b b a SW condition 2 a a a a a a a a a a a a a a a b b b b 3 b b b b b b b b b b b b b b b b b b 4 a a b a a b a a b a a b a a b a a b 5 6 7 8 b b b b b b b b b b b b d d d b b b a -- 230 -- ns 8 10 50 mVrms 7 52 56 dB 6 -40 -25 dB 5 -0.3 0 0.3 dB 4 -2.7 -2 -1.7 -1 0 0 dB 3 -2 0 2 dB 2 Min. Typ. Max. Unit Note
a--a b--a b--a a--a b--a b--a a--a b--a b--a a--a b--a b--a a--a b--a b--a a--a b--a b--a
b ------ a
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CXL1510M
(No signals input to C-IN1, C-IN2) Item Low frequency gain Frequency response Differential gain Differential phase Linearity Symbol GLY1 GLY2 FY1 FY2 DGY1 DGY2 DPY1 DPY2 LNY1 LNY2 SNY1 SN ratio Coupling level SNY2 CPY1 CPY2 (See Note 7) (See Note 10) 50% white video signal (See Note 3) 5-step staircase wave 5-step staircase wave (See Note 2) Measurement condition 1 b b b b b b b b b b b b b b SW condition 2 b b b b b b b b b b b b b b 3 4 5 6 b a b b a a a a a a b b b b 7 b b b b b b b b b b b b b b 8 b b b b c c c c a a d d b b 10 50 mVrms 7 52 56 dB 6 35 40 43 % 10 0 3 5 deg 9 0 3 5 % 9 -2 -1 0 dB 3 Min. Typ. Max. Unit Note
a--a a--b a--a a--b a--a a--b a--a a--b a--a a--b a--a a--b b--a b--b
-2
0
2
dB
2
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CXL1510M
Note 1. This is the IC's supply current value when no signals are input. 2. This is the C-OUT and Y-OUT pin output gain when 500mVp-p sine waves are input to C-IN1, C-IN2 and Y-IN. (Example of calculation) GLC1 = 20 log C-OUT pin output voltage (mVp-p) [dB] 500 (mVp-p)
Input signal frequency GLC1 (2H + 12) GLC2 (2H) GLC3 (1H) GLY1, GLY2
: 203.206kHz : 204.545kHz : 204.545kHz : 200kHz
3. This indicates the difference in the C-OUT and Y-OUT pin output gain when 200mVp-p low- and highfrequency sine waves are input to C-IN1, C-IN2 and Y-IN. Set the input bias (Vbias) to 2.0V when measuring the luminance signal characteristics (GLY1, GLY2, GHY1, GHY2). (Example of calculation) FC1 = 20 log C-OUT pin output voltage (high frequency) (mVp-p) [dB] C-OUT pin output voltage (low frequency) (mVp-p)
Input signal frequency (low frequency) see Note 2 Input signal frequency (high frequency) Chrominance signal (2H + 12) : 4.431446MHz Chrominance signal (2H) : 3.571678MHz Chrominance signal (1H) : 3.571678MHz Luminance system : 3.58MHz 4. Calculate with the gain applying when 200mVp-p and 500mVp-p sine waves (see Note 2 for the frequencies) are input to C-IN1 and C-IN2. (Example of calculation) Output voltage with 500mVp-p input (mVp-p) 500mVp-p Output voltage with 200mVp-p input (mVp-p) 200mVp-p
LIC1 = 20 log
[dB]
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CXL1510M
5. Measure the difference of the C-OUT output gain when 500mVp-p sine waves have been input to C-IN1 and C-IN2 at the following frequencies. Input signal frequency fp 4.431446MHz 3.571678MHz 3.571678MHz fN 4.427538MHz 3.567744MHz 3.563811MHz
CCD1 CCD2 CCD4
The frequency response for the outputs at fp and fN are shown in the figure below.
Gain
fN
fp
Frequency
6. Using the BPF 100kHz to 4MHz in the Sub Carrier Trap mode, measure the SN ratio on the video noise meter when the 50% white video signal shown in the figure below is input.
178mV
321mV
143mV
7. Measure the internal clock component (4fsc: 14.31818MHz component) when no signals are input. 8. Measure the delay time of the C-OUT output when the C-IN1 signal is input.
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CXL1510M
9.
On the vector scope, measure the differential gain and differential phase when the 5-step staircase wave shown in the figure below is input.
143mV
357mV 500mV
143mV
10. Input the 5-step staircase wave only for the luminance signal shown in the figure below, and measure the Y-OUT luminance level (Y) and SYNC level (S). (Example of calculation) LNY1 =
500mV
Y
357mV
S (mV) x 100 Y (mV)
S 143mV
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Electrical Characteristics Measurement Circuit
5V 1k
SW4 0.1 1k 0.1 0.1 82k
a
b
24
23 22 20 21 16 17 15 14
19 18
13
- 10 -
2 3 7 11 4 8 10 5 6 9 12 3.3 1000P a b 1k Vbias SW6 0.01 1M b SW5 a
5V 1k a SW7 b SW8
a Oscilloscope b Spectrum analyzer c LPF d BPF Vector scope Noise meter
1
Signal generator
a SW1
b
0.01
a SW2
b
0.01
a SW3
b
0.1
A
5V
CXL1510M
CLK fsc (3.579545MHz) 0.5Vp-p sine wave
Application Circuit
5V 1k C-OUT CONT1 (0/5V) fsc out
When Pin 20 (fsc) output is used (connect to VDD when not used)
0.1 1k 0.1 0.1 24 23 22 20 21 16 17 15 14 19 18 13 2.2k 82k
CXL1510M
5V 1 2 3 7 4 8 10 5 6 9 11 12 1k Y-OUT
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3.3 1000P 1M CONT2 (0/5V) 5V
C-IN1
0.01
0.01
C-IN2
0.01
Y-IN
0.1 CLK fsc (3.579545MHz) 0.5Vp-p sine wave CXL1510M
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXL1510M
Example of Representative Characteristics
Low frequency gain vs. Supply voltage
2 0
Frequency response vs. Supply voltage
Low frequency gain [dB]
1
Frequency response [dB]
-1 FC2, FC3, FY1, FY2
0
-2 FC1
-1
-2 4.75 5 Supply voltage [V] 5.25
-3 4.75
5 Supply voltage [V]
5.25
Comb depth vs. Supply voltage
-30 0.3
Chrominance linearity vs. Supply voltage
0.2
Chrominance linearity [dB]
5 Supply voltage [V] 5.25
Comb depth [dB]
0.1 0
-35
-0.1
-0.2 -40 4.75 -0.3 4.75
5 Supply voltage [V]
5.25
Differential gain vs. Supply voltage
8 5
Differential phase vs. Supply voltage
4 6
Differential phase [degree]
5 Supply voltage [V] 5.25
Differential gain [%]
3
4
2
2
1
0 4.75
0 4.75 5 Supply voltage [V] 5.25
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CXL1510M
Low frequency gain vs. Ambient temperature
2
Frequency response vs. Ambient temperature
0
Low frequency gain [dB]
1
Frequency response [dB]
-1 FC2, FC3, FY1, FY2
0
-2 FC1
-1
-2 -10
-3 0 10 20 30 40 Ambient temperature [C] 50 60 -10 0 10 20 30 40 Ambient temperature [C] 50 60
Comb depth vs. Ambient temperature
-30
Chrominance linearity vs. Ambient temperature
2
Chrominance linearity [dB]
0 10 20 30 40 50 60
1
Comb depth [dB]
-35
0
-1
-40 -10
-2 -10 0 Ambient temperature [C] 10 20 30 40 Ambient temperature [C] 50 60
Differential gain vs. Ambient temperature
8
Differential phase vs. Ambient temperature
6
4
Differential phase [degree]
-10 0 10 20 30 40 Ambient temperature [C] 50 60
4
Differential gain [%]
2
2
0
0 -10 0 10 20 30 40 Ambient temperature [C] 50 60
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CXL1510M
Package Outline
Unit: mm
24PIN SOP (PLASTIC)
+ 0.4 15.0 - 0.1 24 13
+ 0.4 1.85 - 0.15
0.15
+ 0.3 5.3 - 0.1
7.9 0.4
+ 0.2 0.1 - 0.05
0.45 0.1
1.27
+ 0.1 0.2 - 0.05
0.12 M
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING
COPPER ALLOY / 42ALLOY
0.3g
- 14 -
0.5 0.2
1
12
6.9

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